This invention relates generally to improvements in the fabrication of multi-level complex integrated circuits and relates more particularly to means and methods of interconnecting cells of a wafer having an imperfect yield by interconnecting and routing the signal-connects of cells to master pattern circuit locations in one level of metalization that are compatible with a master pattern of interconnect conductors in a next upper layer of metalization.
In integrated circuit technology, wafers having a nonuniform yield of usable cells have heretofore been interconnected into functional circuit types by producing a plurality of masks tailored for that particular wafer's yield distribution, each mask being associated with an individual alternate layer of dielectric insulation or metalization formed on the wafer.
The first one of these masks was utilized during fabrication to define and form feedthroughs or vias in a first layer of insulation exposing the pads of selected usable cells at the first layer of metalization on the wafer. A second mask was utilized to form a second layer of metalization into conductors associated with the vias in the first layer of insulation and routed into coincidence with via locations which were subsequently formed in a second layer of insulation by a third mask. At least one and possibly more alternate layers of metalization were formed on top on the second layer of insulation and fabricated into interconnect lines and cross-overs as defined by at least a fourth mask whereupon all of the selected usable cells were electrically interconnected into a functionally specified complex integrated circuit type.
Thus, it can be seen that this technique required that the multiple mask for each wafer had to be tailored or laid out for a particular wafer since the yield distribution of usable cells varied from wafer to wafer.